With the increasing utilization of synchronous digital hierarchy (SDH) networks, there is a demand for transmitting the OTN (Optical Transport Network) connection signal ODUk (Optical Channel Data Unit k) in SDH network. In addition, in consideration of the coexistence of OTN and SDH networks, it is also necessary to provide a method of mapping ODUk signal into C-4-Xv (C-4 plus the overhead constitutes the STM-N data) in the form of client data and to transmitting it in a virtual concatenation mode.
ITU-T G.707 standard defines a method of mapping an ODUk signal into a C-4-Xv signal asynchronously, so that the ODUk connection signal may be transmitted in SDH network in VC-4 virtual concatenation mode, that is, ODU1 is mapped into C-4-17C, while ODU2 is mapped into C-4-68v. FIG. 1 shows an actual mapping structure from ODU1 to C-4-17c, wherein D represents payload, R represents fixed padding data, and C represents adjustment opportunity in which CCCCC=00000 indicates that S is a payload, while CCCCC=11111 indicates that S is padding data.
Taking the ODU1 as an example, when ODU1 data are demapped and recovered, an asynchronous clock for ODUI has to be recovered from C-4-17c. The asynchronous mapping and demapping processes will inevitably result in a great deal of mapping and combination jittering. It is known from the definition in G.8251 that OTN services have strict requirements regarding jittering. As a result, a clock recovery scheme is required to filter off the jittering so as to ensure the clock performance.
An existing implementation to filter off jittering and ensure the performance of clock is shown in FIG. 2, in which a writing control module generates a gapped clock in accordance with the actual data and the corresponding clock signal, removes the overhead and padding bits from STM-N (Synchronous Transport Module Level N), and writes the actual ODU1 data into an FIFO (Fist In First Out) queue. In addition, the gapped clock is input into a phase lock loop (PLL) constituted by the serially connected phase discriminator (PD), low pass filter (LPF), and voltage controlled oscillator (VCO). The PLL performs a phase locking to the gapped clock to obtain the current ODU1 clock, i.e., the demapping clock signal.
The detailed procedure of the above described phase locking is: the PD produces a phase difference between the gapped clock and the ODU1 clock fed back by the VCO, in which the phase difference reflects the current difference between the data written into the FIFO and the data read out from the FIFO. In order to balance between the data written into FIFO and the data read from FIFO, the PD sends the phase difference into the LPF for low pass filtering so as to produce a corresponding signal. This signal is sent to the VCO as the control signal for adjusting ODU1 clock frequency output from the VCO, so as to control the ODU1 clock output from VCO to keep track of the gapped clock, thereby balancing the ODU1 clock with the gapped clock.
Since there are not only fixed bits of padding data but also asynchronous data rate adjusting and controlling bits, as well as a great deal of overhead, in STM-N, it is difficult to suppress jittering in an actually output ODU clock by only utilizing one PLL to adjust ODU1 clock directly, and thus it is difficult to meet the requirement for OTN jittering in G.8251.